Abstract:
Recent significant booming in high performance computing (HPC), represented by generative AI, is leading semiconductor market growth. The HPC/AI technology is enabled by so-called advanced packaging technologies such as 2.5D interposer and 3D chip stacking for system level integration, together with advanced silicon technology where traditional scaling is being pursued.
Regarding the advanced packaging, TSMC offers technology suites called “3DFabric” to support wide range of customer demands. 3DFabric includes CoWoS (Chip-on-Wafer-on-Substrate) and InFO (Integrated Fan-Out) which are based on back-end packaging technology, and SoIC (System-on-Integrated-Chip) based on front-end silicon technology. Amongst them, CoWoS is widely being adopted by numerous HPC/AI products as a platform technology for the system level integration. Thus, continuous innovations in CoWoS process and material and their seamless implementation in high volume manufacturing (HVM) are indispensable to realize unremitting evolution of HPC/AI technologies in the future.
TSMC Japan 3DIC R&D Center is established in 2021 to drive future process and material pathfinding for advanced packaging together with ecosystem partners in Japan. In this talk, we will describe the latest progress of this collaborative research focusing on on-Substrate materials, and future outlook of the technologies will be also discussed.

Abstract:
In the rapidly evolving field of artificial intelligence (AI), semiconductor packaging (PKG) technology plays a critical role in meeting the high-performance and efficiency demands of AI systems. As AI applications continue to proliferate across various industries, there is a pressing need for advanced PKG solutions that can accommodate increased computational power, higher data transfer rates, and greater energy efficiency. This discussion will review the development trends in PKG technology, identify core future technologies, and explore specific trends related to high-bandwidth memory (HBM) and heterogeneous chip integration, with a focus on SK hynix's strategic directions.

Abstract:
Chiplet are fundamental to the continued economic growth. New heterogeneous architectures like 2.5D&3D driving AMD’s leading advanced roadmap, will be discussed. And focus on how advanced 3D packaging is enabling industry’s best AI architectures.

Abstract:
AI and other high-performance applications are demanding more from advanced semiconductor packaging. Lower latency, higher bandwidth, and higher density interconnect are all required to support AI.

One way to meet these requirements is with chiplets. Chiplets avoid the reticle and yield limitations that affect traditional monolithic SoCs while also enabling faster signal throughput with less power. Two packaging technologies that support chiplets are interposer-based processes (2.5D) and 3D stacking. Both technologies are complex with many moving parts: chiplets must be obtained, possibly from multiple sources, and they must be stacked and/or placed on an interposer, which itself involves expensive processing to create. The resulting stack must be placed on a substrate, which may be large and complex to meet product requirements.

This talk will present cost breakdowns for 2.5D and 3D advanced packaging technologies. Understanding the cost for each process—starting with the cost of the silicon chiplets and including all manufacturing required to end with a complete package—is imperative. When the cost-prohibitive portions of a technology are identified, the industry is able to focus on solutions and more quickly enable successful AI and high-performance chips.

Abstract:
With the progress of CASE, the intellectualization, computerization, and electrification of automobiles have greatly advanced, and the software and electronic systems installed in them have become large in scale. High-performance digital semiconductors, SoCs are important for controlling these systems in an integrated manner. Because there are variations and circuit scales difference in Japanese cars, the current problem is that SoCs from different vendors are used, the same software cannot be used, software changes must be made to match the hardware, and development costs are enormous. ASRA, Advanced Soc Research for Automotive, aims to create a SoC hardware platform and ecosystem that realize SDV by providing the same software environment from compact cars to luxury cars using chiplet technology. Chiplet SoCs have begun to be put into practical use in data centers, etc., but in automobiles, there are unique technical issues such as functional safety, heat, noise, and vibration. There is no connection technology or packaging technology for automotive chiplets, and new technological development is required. In addition to member companies, ASRA will develop these technologies in cooperation with industry, academia, and government. This project, supported by the Ministry of Economy, Trade and Industry and NEDO, is scheduled to start in 2024, with the chiplet technologies established by 2028 and installed in 2030 vehicles.

Abstract:
Software Defined Vehicles enabled by electric/electronic (E/E) and software architecture will play a vital role in automotive and semiconductor value chain. Automotive E/E architectures have evolved from decentralized approach to Zonal Controllers and Central Compute Units which drive Silicon consolidation and integration. Emerging designs bring together CPUs, memory and hardware accelerators based on advanced Silicon nodes. With the adoption of advanced semiconductor nodes, the automotive industry is facing challenges on how to maintain overall costs. While chiplet adoption is expanding in many applications ranging from high performance computing to consumer electronics, automotive electronics is a special case with different constraints and reliability requirements. The presentation will discuss motivation for utilizing chiplets in automotive applications and opportunities from product configurability, design flexibility and time to market. Additionally, update on two fanout package solutions for automotive applications will be shared - one for multi-SoC/chiplets integration, and another for SoC-HBM3 integration. Both packages utilize ASE VIPackTM FOCoS (Fanout Chip on Substrate)-Chip Last technology.

Abstract:
The automotive industry is undergoing a transformative shift towards electrification, autonomy, and connectivity, demanding unprecedented levels of computational power, energy efficiency, and scalability. Chiplet-based architectures have the potential to revolutionize this sector by addressing these challenges through modular, cost-effective, and high-performance semiconductor solutions. Unlike traditional monolithic system-on-chips (SoCs), chiplets decompose complex designs into smaller, specialized components that can be independently optimized and integrated. We will discuss the drivers for this change for automotive applications, the technology challenges and the implications on design methodology and supply chain.