2017 International Conference on Electronics Packaging
submission deadline is October
In an effort to improve the conference quality, we would like to ask you to prepare an abstract using the attached template to help us better evaluate your submission. The abstract should contain about 1 page of text and 1 page for supporting figures and tables, with a total length of 2 pages at maximum.
Figures and tables to support the point of the paper will receive positive considerations. Technical experts assigned by the conference technical committee will review your abstract, and their comments will be used in the selection process.
Your abstract will be used for review purpose only and will not be included in the conference proceeding.
Thank you very much for your contribution!
Abstract Template click here
Call for papers click here
Final manuscript of two to six pages should be submitted by January 31,
2017, for both oral and poster presentations.
*Only full papers (4-6 pages in conference format) submitted by the due date will be considered for the conference Awards.
Accepted and presented papers will be published in the conference proceedings and submitted to IEEE Xplore as well as other Abstracting and Indexing (A&I) databases (EI Compendex and INSPEC).
Member of JIEP / IEEE / IMAPS: 41,000 yen (including reception and the
Non Member: 55,000 yen (including reception and the proceedings)
Students: 12,000 yen (including the proceedings)
|1. Advanced Packaging
Wafer Level Packaging, System Integration, PoP, MCM, System on Package, Novel Assembly Technologies
|2. Substrate and Interposers
Laminates, Interposers, Fine Pitch, Build-up Substrates, Flexible Printed Circuits, Embedded, Conductive Paste, Thin Core, Coreless, Low CTE
Bump Formation, Chip-Package Interaction, Low k, Leadframe, Test of First- and Second- Level Interconnections, Interconnections for 3D Integration, Interconnections in Substrates, PCBs and Systems
|4. 3DIC Packaging
TSV, Via Formation and Filling, 2.5D, Wafer Thining, Silicon Stacking, Chip on Chip, Chip on Wafer, Wafer on Wafer, Wide Bus, Wireless Interconnection, Temporary Bonding/De-Bonding
|5. Design, Modeling,
Signal and Power Integrity, High Speed Board Design, Mechanical Design and Reliability, Failure Analysis, Fracture and Warpage in Packages, Testing, Evaluation, TCAD, 3DIC Design
|6. Thermal Management
Advanced Cooling Modules, Heat Pipes, Heat Sinks, Fans and Blowers, Thermal Interface Materials, Thermal Measurements, Micro and Nano Scale Heat Transfer, Thermal Issues in Devices
|7. Materials and
Novel Materials and Processing, Dielectrics, Emerging Materials and Processes for 3D, Thin Films, Underfills, Assembly Challenges and Solutions, Wefer Thinning, Plating, Equipment, Encapsulation
|8. Printed Electronics
Inkjet, Screen Printing, Conductive Wiring, Insulation, Printed Organic TFTs, Device Applications
NEMS-MEMS/Sensor Devices, MOEMS, Assembly and Packaging, Nano Technology, Nano Imprint Lithography, Organic Semiconductors, Wireless Sensor Networks
Active Optical Cable, Photonic Devices, Optical Fibers, Waveguides, Optical Interconnects, Transceivers, Connectors, LD/PD, LED, OE/EO, TOSA/ROSA, WDM, Optical Wiring Boards
Biomimetics, Nature-Guided, Bottom-up Manufacturing, Smart Materials and Devices, Spontaneous Ordering/Patterning/Structuring, Self-Bonding/Debonding, Repairable, Self-Healing, Novel Micro/Nano Processing
|12. Medical Devices
Invasive, Low Invasive, Non Invasive, In Vitro, BAN, Cure, Treatment, Diagnosis, Screening, POC, Healthcare
Si, SiC or GaN Power Device/Module Packaging; Packaging of High-temperature Power Electronics, Sensors; Inverters/Converters for Electric Vehicles; Magnetic Materials and Components; Substrate Technologies; Encapsulation Materials; PE Integration by 3D Printing
RFID, High Frequency Devices, Packaging, Filters, EMI, EMC, Antennas, Wireless Power Transmission
Market Trends, Environmentally Conscious Products and Processes, Cost Analyses