Keynote Lectures

Chip-Package Interaction on High Bandwidth Memory (HBM)

Naoki Yokoi
Micron Memory Japan KK

Session time：
April 15 (Wed) 15:40 - 16:40

Abstract:
High Bandwidth Memory (HBM) has become a foundational technology for high performance computing, particularly in artificial intelligence (AI) and deep learning accelerators. As HBM adoption accelerates, system in package (SiP) integration plays increasingly critical roles in meeting bandwidth, power efficiency, and capacity requirements.

An HBM stack is formed by vertically integrating multiple DRAM dies on a logic base die, interconnected through through-silicon vias (TSVs). Multiple HBM stacks are then integrated with a processor on a silicon interposer using fine pitch, high density wiring to construct the final SiP. Manufacturing these modules requires sophisticated backend processes—many performed after wafer completion—which underscores the strong coupling between silicon technology, TSV formation, and advanced packaging.

As memory capacity and performance targets continue to rise, both the number of DRAM dies within each HBM stack and the number of stacks within a single SiP are increasing. At the same time, processors impose rapidly escalating requirements for power efficiency and operating speed. Meeting these objectives demands a deep understanding of chip–package interaction on device performance and reliability.

This presentation introduces the structural and architectural features of HBM that enable next generation high performance computing. It reviews key manufacturing steps involved in constructing SiPs with HBM stacks. Finally, the talk emphasizes the importance of co optimizing silicon processes and packaging technologies to ensure reliable, high performance HBM solutions.

Enabling AI compute hardware through Silicon Photonics and advanced 3D assembly technologies

Ossieur, Peter
imec

Session time：
April 15 (Wed) 16:40 - 17:25

Abstract:
The need for compute supporting AI and machine learning applications continues to grow at a staggering exponential rate. The performance of this hardware is critically dependent on the fabric that interconnects the processing units and memory into a coherent compute cluster. Conventional so-called scale-out networks are used to interconnect racks of compute hardware, and today rely on pluggable modules. To save power, it is expected that a move to co-packaged optics (CPO) will be critical, requiring both optics and electronics with sufficiently small footprint to fit the smaller area available in such solutions. While such CPO solutions would initially still rely on fast-and-narrow optical links (400G/lane, requiring ultra broadband optics and electronics), in the future also these solutions will not meet strict requirements on energy consumption and shoreline density. An alternative is to combine advanced assembly technologies such as hybrid bonding with integrated photonics to create wide-and-slow optical interfaces. Close co-development of photonics and electronics is crucial to minimize power consumption. It will be shown how advanced assembly and integrated photonics technologies can be used to create optical transceivers with very high shoreline densities and low energy consumption, rivaling short-reach die-to-die interconnect but with significantly longer reaches. Such solutions can be used for both fiber interconnect extending so-called scale-up networks beyond a single rack, but also wafer-level optical interconnect to create high capacity links between processing units assembled onto interposer wafers.

Advanced Thinning and Cutting Technologies Enabling AI-Oriented Heterogeneous Integration

Youngsuk Kim
DISCO Corp.

Session time：
April 16 (Thu) 08:30 - 09:15

Abstract:
Heterogeneous integration technologies, including 2.5D/3D integration, hybrid copper bonding, fan-out (FO) wafer-level packaging (WLP), and panel-level packaging (PLP), have emerged as promising approaches to enhance device performance and integration density beyond conventional scaling. These advanced packaging schemes require substantial modifications to device architectures and manufacturing processes, which in turn elevate the importance of grinding and dicing technologies. To enable high-performance and high-yield heterogeneous integration, process optimizations such as ultra-thinning and high-precision cutting are critical. This presentation will discuss the current technical challenges and outlines future directions and potential solutions for grinding and dicing technologies in advanced packaging.

The Future of Computing

Norishige Morimoto
IBM Japan, Ltd.

Session time：
April 17 (Fri) 09:00 - 09:45

Abstract:
AI is no longer just a tool; it is becoming the core infrastructure driving technological and societal transformation. The rapid growth and adoption of AI technologies across industries show no sign of slowing down. Analyses show that the computational demands for AI have increased by a factor of 100 million in just 15 years. These advances bring new societal challenges that require innovative solutions.

IBM is exploring three key areas: Bits, Neurons, and Qubits. Bits represent advances in semiconductor technology, where continuous chip miniaturization enables cost efficiency, reduced power consumption, and enhanced computing capability. Neurons refer to next-generation AI chips inspired by the human brain, promising dramatic improvements in performance and energy efficiency. Qubits introduce quantum computing, which opens doors to entirely new scientific and technological frontiers through quantum-centric supercomputing techniques.

These technologies work together and complement each other to form the foundation of IBM’s vision for the future of computing. In this session, we will provide an overview of these innovations and share the latest updates on how they work together and complement each other to create new possibilities for the future of technology and our society.